South Korea-based XCENA is redefining data centre architecture for the upcoming AI era through a unique technology: computational memory technology that merges high-capacity pooled DDR5 memory with near-data processing (NDP) cores.
As per the start-up, XCENA’s technology, built on the open Compute Express Link (CXL) standard, expands a computer’s memory beyond traditional CPU limits, apart from executing computation where data resides, reducing latency, energy use and total cost of ownership.
Founded by semiconductor veterans from Samsung and SK Hynix (South Korean semiconductor major), XCENA combines deep hardware expertise with a full-stack software SDK to enable rapid deployment and seamless workload acceleration for hyperscalers, telcos, and research institutions.
In today’s episode of the “Start-up of the Week”, International Finance will talk in detail about XCENA, which, by bridging the gap between compute and memory, is powering a new class of intelligent, efficient, and scalable AI infrastructure.
Addressing AI’s data relay bottleneck
Every prompt, every question asked to ChatGPT, starts a data relay race where information leaves memory, passes through a CPU for preprocessing, travels to a GPU (Graphics Processing Unit) for heavy computation, and then makes its way back to the user in the form of “AI-generated replies”.
XCENA sees this as a structural bottleneck, which results in data routing through some of the most expensive and power-intensive chips in the industry on every single user prompt. To solve this, the four-year-old company, with a secondary presence in the United States, has come up with a chip that places compute capabilities much closer to DRAM (Dynamic Random-Access Memory). DRAM is known as the type of volatile computer memory used as the main memory (RAM) in PCs, laptops, and smartphones that temporarily stores data that users’ CPUs need to actively run programs and apps.
XCENA is using DRAM, the fast, short-term memory chips, as the main mechanism enabling routine data operations to be handled near memory without the costly round data trips between CPUs, GPUs, and memory. XCENA was in the news in the first week of June 2026 by raising USD 135 million in a Series B at a valuation of USD 570 million, which brought its total capital raised to USD 185 million.
XCENA CEO Jin Kim co-founded the start-up in 2022 alongside CTO Dohun Kim and CPO Harry Juhyun Kim, veterans of Samsung and SK Hynix, the memory giants also known for supplying chips powering Nvidia’s GPUs.
CPUs and GPUs have both gotten smarter over the decades. Memory never did. XCENA wants to change that. The recent rise in memory prices and related stocks points to a broader shift in AI infrastructure toward memory-centric architectures,” Jin Kim told TechCrunch.
While the chipmaking trio of Samsung, SK Hynix, and Micron crossed a trillion-dollar valuation for the first time, further consolidating their hold on the global semiconductor ecosystem, XCENA is taking a different path by putting all of its money on inference, which, as per Kim, “is increasingly becoming a memory scaling problem.”
The World’s First CXL 3.2 Computational Memory
XCENA’s chip, the MX1, connects to the CPU through CXL (Compute Express Link), becoming a dedicated express lane in the process between the processor and memory by processing data before it ever needs to leave the memory module. The breakthrough technology brings compute to the data, not the other way around. As per the start-up, what used to require 10 servers could potentially run on just one.
“While GPUs excel at matrix multiplication — the heavy math behind AI model training — much of the surrounding data orchestration, including preprocessing, KV cache management (the system that stores prior conversation context so a model doesn’t have to reprocess it), and data caching, still runs on CPUs. Our chip handles those tasks directly within the memory module itself,” Kim said.
MX1, the world’s first computational memory controller supporting CXL 3.2, is built to break the memory wall in AI data centres. It integrates up to 2 TB of DDR5 memory with thousands of RISC-V cores for near-data processing, reducing data movement and computation.
workload. MX1 also supports PCIe 6.0 SSD-backed expansion, enabling scalable and cost-efficient memory for large-scale AI workloads. “The company explained its breakthrough product through these following words.
Among the core features of the MX1, we have CXL memory expansion, with the chip enabling memory expansion up to 2 TB via CXL. The functions achieve up to 128 GB/s bandwidth over PCIe 6.0. The chip also maximises system efficiency by reducing unnecessary data movement in AI and HPC (High-Performance Computing) applications.
MX1 also brings “near-data processing” capability, as thousands of RISC-V cores process data near memory, reducing CPU load and latency. The chip has been optimised for data-intensive workloads such as AI inference, RAG, vector databases, and KV cache.
The chip also possesses enhanced RAS (Reliability, Availability, and Serviceability) features like Chipkill, SSD RAID, and ECC for fault recovery and data integrity. These capabilities ensure high availability and serviceability for mission-critical environments like data centres.
MX1’s “memory compression” supports software-based compression and hardware-based decompression by reducing overall cost by allowing more data to be stored and processed in the same physical footprint.
MX1’s scalable architecture, combining DRAM and PCIe 6.0 SSDs, enables petabyte-scale memory by minimising latency while maximising capacity through DRAM caching.
And last but not least, MX1 also provides developer-friendly tools across all layers, including runtime. It offers an integrated software environment optimised for various workloads, including SQL (Structured Query Language), vector processing, and graph analytics.
All set for the mass production stage
As the AI wave becomes the new normal in the tech industry, the demand for memory solutions has surged since the second half of 2025. XCENA is reportedly in touch with several global memory vendors. The company is eyeing the hyperscalers as its ideal customers. While these hyperscalers are spending tens of billions a year on AI infrastructure, XCENA believes, through MX1, even a small gain in memory efficiency will bring hundreds of millions in savings for these companies.
While the flagship product itself has been in the prototype stage, mass production is scheduled to roll off Samsung’s foundry lines by the 2026-end, with the company eyeing revenue flow from 2027 onwards. While neural processing unit (NPU) makers are looking to become the competitors for chipmaking giant Nvidia when it comes to training workloads, XCENA is taking a different but a crucial path altogether: targeting the memory-intensive layer that sits underneath all of the AI chip ecosystem.
It’s not like XCENA doesn’t have rivals. It needs to compete with Nasdaq-listed Astera Labs and Marvell, both working on next-generation memory connectivity. While Marvell is a large, established player, the start-up has thousands of cores. Based on publicly available specifications, Marvell’s approach relies on a handful of general-purpose cores by comparison. So XCENA is looking to win the game here through sheer numbers.
XCENA’s cores are built on RISC-V, an open-source chip design blueprint optimised specifically for data processing. Beyond the cores (tailored as small and efficient beings), XCENA designs its own internal memory hierarchy, interconnect bus, and DRAM controller and research and development activities, which its rivals mostly outsource.